[Customized Model] ESD/CDM Pulse Simulator | Ecdm-400S-TLP

Test & Measurement Technology

ESD/CDM Pulse Simulator Ecdm-400S-TLP

Model Ecdm-400S-TLP

Applying HBM, MM or CDM (F-CDM or D-CDM) stress to the bonding pads of bigger IC die via contacy needles on the manipulators, endurance can be measured against them. Damage is detected by the other IC tester or siplme source meter. Low cost system is expected though manual operation. Wafer test may be possible as well as sliced die test. TLP configuration is also available.

Lower level ESD stressor

In these days, very ESD sensitive devices such as MR head and GaAs IC are increasing. To measure the ESD sensitivity of these devices, traditional ESD stressor for IC and LSI is not suitable. Device may be damaged by only contact of probe pin to the DUT or by relay noise in ESD generator. Ecdm-100E/400E can be trimmed for these extremely sensitive applications. Especially, trimmed Ecdm-100E is well accepted in the MR head applications. HBM, MM, CDM(Field induced CDM and Direct Charging CDM) are available.

TLP configuration

I-V curve measurement using short width TLP (Transmission Line Pulse) is popular as the characterization procedure of the ESD protection element. Ecdm100E/400E can be configured for this application. Though manual measurement is standard, GP-IB maybe specified so that PC controlled test and curve plot may be possible if you develop your own program.


  • Voltage : 4kV (max)
  • Ip Pulse : 0 to 6A
  • Vp Pulse : 0 to 2kV
  • Leak measurement : 0 to 30V / 10nA
  • Probe : TLP (WT-6NM)
  • Pulse rise : 10nS
  • Pulse width : 50, 100, 150, 200ns
  • Option : X-Y stage
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